#ifndef _REGS_H
#define _REGS_H
/*
  author Sylvain Bertrand <digital.ragnarok@gmail.com>
  Protected by GNU Affero GPL v3 with some exceptions.
  See README at root of alga tree.
*/

/*
 * many masks are 0xfffffff because we need the info from AMD
 * or need to deduce from other values in the register
 */

#define SET(n, x) (((x) << n##_SHIFT) & n##_MASK)
#define GET(n, x) (((x) & n##_MASK) >> n##_SHIFT)

#define	PCIE_PORT_INDEX				0x38
#define	PCIE_PORT_DATA				0x3c

#define RCU_IDX					0x100
#define RCU_DATA				0x104

#define	SRBM_STATUS				0xe50
#define 	MC_STATUS_MASK				0x00001f00
#define		MC_STATUS_SHIFT				8

#define VM_L2_CTL_0				0x1400
#define		ENA_L2_CACHE				BIT(0)
#define		ENA_L2_FRAG_PROCESSING			BIT(1)
#define		ENA_L2_PTE_CACHE_LRU_UPDATE_BY_WR	BIT(9)
#define		EFFECTIVE_L2_QUEUE_SZ_MASK		0x0001c000			
#define		EFFECTIVE_L2_QUEUE_SZ_SHIFT		14
#define VM_L2_CTL_1				0x1404
#define		INVALIDATE_ALL_L1_TLBS			BIT(0)
#define		INVALIDATE_L2_CACHE			BIT(1)
#define VM_L2_CTL_2				0x1408
#define		BANK_SELECT_MASK			0xffffffff
#define		BANK_SELECT_SHIFT			0
#define		CACHE_UPDATE_MODE_MASK			0xffffffff
#define		CACHE_UPDATE_MODE_SHIFT			6

#define	VM_L2_STATUS				0x140c
#define		L2_BUSY					BIT(0)

#define VM_CTX_0_CTL				0x1410
#define		ENA_CTX					BIT(0)
#define		PT_DEPTH_MASK				0x00000006
#define		PT_DEPTH_SHIFT				1
#define		RNG_PROTECTION_FAULT_ENA_DEFAULT	BIT(4)
#define VM_CTX_1_CTL				0x1414

#define VM_CTX_0_REQ_RESP			0x1470
#define		REQ_TYPE_MASK				0x0000000f
#define		REQ_TYPE_SHIFT				0
#define			TLB_FLUSH				1
#define		RESP_TYPE_MASK				0x000000f0
#define		RESP_TYPE_SHIFT				4
#define			RESP_FAILED				2

#define VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
#define	VM_CTX_0_PT_BASE_ADDR			0x153c
#define	VM_CTX_0_PT_END_ADDR			0x157c
#define	VM_CTX_0_PT_START_ADDR			0x155c

#define MC_SHARED_CHMAP				0x2004
#define		CHANS_N_MASK				0x00003000
#define		CHANS_N_SHIFT				12
#define MC_SHARED_CHREMAP			0x2008

#define	MC_VRAM_LOCATION			0x2024 /* 16MB aligned */

#define	MC_AGP_TOP				0x2028 /* 4MB aligned */
#define	MC_AGP_BOT				0x202c /* 4MB aligned */
#define	MC_AGP_BASE				0x2030

#define	MC_VM_SYS_APER_LOW_ADDR			0x2034
#define	MC_VM_SYS_APER_HIGH_ADDR		0x2038
#define	MC_VM_SYS_APER_DEFAULT_ADDR		0x203c

/* MB acronym unknown */
#define	MC_VM_MB_L1_TLB_0_CTL			0x2234
#define	MC_VM_MB_L1_TLB_1_CTL			0x2238
#define	MC_VM_MB_L1_TLB_2_CTL			0x223C
#define	MC_VM_MB_L1_TLB_3_CTL			0x2240
#define		ENA_L1_TLB				BIT(0)
#define		ENA_L1_FRAG_PROCESSING			BIT(1)
#define		SYS_ACCESS_MODE_MASK			0x00000018
#define		SYS_ACCESS_MODE_SHIFT			3
#define			PA_ONLY					0
#define			USE_SYS_MAY				1
#define			IN_SYS					2
#define			NOT_IN_SYS				3	
#define		SYS_APER_UNMAPPED_ACCESS_MASK		0xffffffff
#define		SYS_APER_UNMAPPED_ACCESS_SHIFT		5
#define			PASS_THRU				0
#define		EFFECTIVE_L1_TLB_SZ_MASK		0xffffffff
#define		EFFECTIVE_L1_TLB_SZ_SHIFT		15
#define		EFFECTIVE_L1_QUEUE_SZ_MASK		0xffffffff
#define		EFFECTIVE_L1_QUEUE_SZ_SHIFT		18

/* MD acronym unknown, see MC_VM_MB_L1_TLB*_* regs */
#define	MC_VM_MD_L1_TLB_0_CTL			0x2654
#define	MC_VM_MD_L1_TLB_1_CTL			0x2658
#define	MC_VM_MD_L1_TLB_2_CTL			0x265c
#define	MC_VM_MD_L1_TLB_3_CTL			0x2698

#define	MC_ARB_RAM_CFG				0x2760
#define		MC_BANKS_N_SHIFT			0
#define		MC_BANKS_N_MASK				0x00000003
#define		MC_RANKS_N_SHIFT			2
#define		MC_RANKS_N_MASK				0x00000004
#define		MC_ROWS_N_SHIFT				3
#define		MC_ROWS_N_MASK				0x00000038
#define		MC_COLS_N_SHIFT				6
#define		MC_COLS_N_MASK				0x000000c0
#define		CHAN_SZ_SHIFT				8 /* 64 or 32 bits */
#define		CHAN_SZ_MASK				0x00000100
#define		BURST_LEN_SHIFT				9
#define		BURST_LEN_MASK				0x00000200
#define		CHAN_SZ_OVERRIDE			BIT(11)

#define	HDP_HOST_PATH_CTL			0x2c00
#define	HDP_NONSURFACE_BASE			0x2c04
#define	HDP_NONSURFACE_INFO			0x2c08
#define	HDP_NONSURFACE_SZ			0x2c0c

#define HDP_ADDR_CFG 				0x2f48
#define HDP_MISC_CTL				0x2f4c
#define		HDP_FLUSH_INVALIDATE_CACHE		BIT(0)

/*
 * HDP data
 * 0x2c14 - 0x2f27 32 blocks of 0x18 bytes
 */

#define IH_RB_CTL				0x3e00
#define		IH_RB_ENA				BIT(0)
#define		IH_IB_LOG2_DWS_MASK			0xffffffff
#define		IH_IB_LOG2_DWS_SHIFT			1
#define		IH_RB_FULL_DRAIN_ENA			BIT(6)
#define		IH_WPTR_WRITEBACK_ENA			BIT(8)
#define		IH_WPTR_WRITEBACK_TIMER_MASK		0xffffffff
#define		IH_WPTR_WRITEBACK_TIMER_SHIFT		9
#define		IH_WPTR_OVERFLOW_ENA			BIT(16)
#define		IH_WPTR_OVERFLOW_CLR			BIT(31)
#define IH_RB_BASE				0x3e04
#define IH_RB_RPTR				0x3e08
#define IH_RB_WPTR				0x3e0c
#define		RB_OVERFLOW				BIT(0)
#define		WPTR_OF_MASK				0x3fffc
#define IH_RB_WPTR_ADDR_HI			0x3e10
#define IH_RB_WPTR_ADDR_LO			0x3e14
#define IH_CTL					0x3e18
#define		ENA_INTR				BIT(0)
#define		IH_MC_SWAP_MASK				0x00000006
#define		IH_MC_SWAP_SHIFT			1
#define			IH_MC_SWAP_NONE				0
#define			IH_MC_SWAP_16BIT			1
#define			IH_MC_SWAP_32BIT			2
#define			IH_MC_SWAP_64BIT			3
#define		RPTR_REARM				BIT(4)
#define		MC_WR_REQ_CREDIT_MASK			0xffffffff
#define		MC_WR_REQ_CREDIT_SHIFT			15
#define		MC_WR_CLEAN_CNT_MASK			0xffffffff
#define		MC_WR_CLEAN_CNT_SHIFT			20

#define RLC_CTL					0x3f00
#define		RLC_ENA					BIT(0)
#define RLC_HB_BASE				0x3f10
#define RLC_HB_CTL				0x3f0c
#define RLC_HB_RPTR				0x3f20
#define RLC_HB_WPTR				0x3f1c
#define RLC_HB_WPTR_LSB_ADDR			0x3f14
#define RLC_HB_WPTR_MSB_ADDR			0x3f18
#define RLC_MC_CTL				0x3f44
#define RLC_UCODE_CTL				0x3f48
#define RLC_UCODE_ADDR				0x3f2c
#define RLC_UCODE_DATA				0x3f30

#define	CC_SYS_RB_BACKEND_DIS			0x3f88

#define	CGTS_SYS_TCC_DIS			0x3f90
#define	CGTS_USER_SYS_TCC_DIS			0x3f94

#define RLC_GFX_IDX           			0x3fc4 /* see GRDBM_GFX_IDX */

#define	CFG_MEM_SZ				0x5428 /* unit is MB */

#define INTR_CTL				0x5468
#define		IH_DUMMY_RD_OVERRIDE			BIT(0)
#define		IH_DUMMY_RD_ENA				BIT(1)
#define		IH_REQ_NONSNOOP_ENA			BIT(3)
#define		GEN_IH_INT_ENA				BIT(8)
#define INTR_CTL2				0x546c

#define HDP_MEM_COHERENCY_FLUSH_CTL		0x5480 
#define HDP_REG_COHERENCY_FLUSH_CTL		0x54a0

/* start of configuration register area: 0x8000-0xac00 */
#define	GRBM_CTL				0x8000
#define		GRBM_RD_TIMEOUT_MASK			0xffffffff
#define		GRBM_RD_TIMEOUT_SHIFT			0
#define	GRBM_STATUS				0x8010
#define		CMDFIFO_AVAIL_MASK			0x0000000f
#define		SRBM_RQ_PENDING				BIT(5)
#define		CF_RQ_PENDING				BIT(7)
#define		PF_RQ_PENDING				BIT(8)
#define		GRBM_EE_BUSY				BIT(10)
#define		SX_CLEAN				BIT(11)
#define		DB_CLEAN				BIT(12)
#define		CB_CLEAN				BIT(13)
#define		TA_BUSY 				BIT(14)
#define		VGT_BUSY_NO_DMA				BIT(16)
#define		VGT_BUSY				BIT(17)
#define		SX_BUSY 				BIT(20)
#define		SH_BUSY 				BIT(21)
#define		SPI_BUSY				BIT(22)
#define		SC_BUSY 				BIT(24)
#define		PA_BUSY 				BIT(25)
#define		DB_BUSY 				BIT(26)
#define		CP_COHERENCY_BUSY      			BIT(28)
#define		CP_BUSY 				BIT(29)
#define		CB_BUSY 				BIT(30)
#define		GUI_ACTIVE				BIT(31)
#define	GRBM_STATUS_SE0				0x8014
#define	GRBM_STATUS_SE1				0x8018
#define		SE_SX_CLEAN				BIT(0)
#define		SE_DB_CLEAN				BIT(1)
#define		SE_CB_CLEAN				BIT(2)
#define		SE_TA_BUSY				BIT(25)
#define		SE_SX_BUSY				BIT(26)
#define		SE_SPI_BUSY				BIT(27)
#define		SE_SH_BUSY				BIT(28)
#define		SE_SC_BUSY				BIT(29)
#define		SE_DB_BUSY				BIT(30)
#define		SE_CB_BUSY				BIT(31)

#define	GRBM_SOFT_RESET				0x8020
#define		SOFT_RESET_CP				BIT(0)
#define		SOFT_RESET_CB				BIT(1)
#define		SOFT_RESET_DB				BIT(3)
#define		SOFT_RESET_PA				BIT(5)
#define		SOFT_RESET_SC				BIT(6)
#define		SOFT_RESET_SPI				BIT(8)
#define		SOFT_RESET_SH				BIT(9)
#define		SOFT_RESET_SX				BIT(10)
#define		SOFT_RESET_TC				BIT(11)
#define		SOFT_RESET_TA				BIT(12)
#define		SOFT_RESET_VC				BIT(13)
#define		SOFT_RESET_VGT				BIT(14)

#define GRBM_GFX_IDX				0x802c
#define		INST_IDX_MASK				0xffffffff
#define		INST_IDX_SHIFT				0
#define		SE_IDX_MASK				0xffffffff
#define		SE_IDX_SHIFT				16
#define		INST_BROADCAST_WRS			BIT(30)
#define		SE_BROADCAST_WRS			BIT(31)

#define GRBM_INT_CTL				0x8060
#define		RD_ERR_INT_ENA				BIT(0)
#define		GUI_IDLE_INT_ENA			BIT(19)

/* not yet used in the code
#define	SCRATCH_REG0	0x8500
#define	SCRATCH_REG1	0x8504
#define	SCRATCH_REG2	0x8508
#define	SCRATCH_REG3	0x850c
#define	SCRATCH_REG4	0x8510
#define	SCRATCH_REG5	0x8514
#define	SCRATCH_REG6	0x8518
#define	SCRATCH_REG7	0x851c
*/
#define	SCRATCH_UMSK				0x8540
#define	SCRATCH_ADDR				0x8544

#define	CP_SEM_WAIT_TIMER			0x85bc

#define CP_ME_CTL				0x86d8
#define		CP_ME_HALT				BIT(28)
#define		CP_PFP_HALT				BIT(26)

#define	CP_RB_RPTR				0x8700
#define	CP_RB_WPTR_DELAY			0x8704

#define	CP_QUEUE_THRESHOLDS			0x8760
#define		ROQ_IB1_START_MASK			0xffffffff
#define		ROQ_IB1_START_SHIFT			0
#define		ROQ_IB2_START_MASK			0xffffffff
#define		ROQ_IB2_START_SHIFT			8

#define CP_MEQ_THRESHOLDS			0x8764
#define		STQ_SPLIT_MASK				0xffffffff
#define		STQ_SPLIT_SHIFT				0

#define	CP_PERFMON_CTL				0x87fc

#define	VGT_CACHE_INVALIDATION			0x88c4
#define		CACHE_INVALIDATION_MASK			0x00000003
#define		CACHE_INVALIDATION_SHIFT		0
#define			VC_ONLY					0
#define			TC_ONLY					1
#define			VC_AND_TC				2
#define		AUTO_INVALIDATION_ENA_MASK		0x000000c0
#define		AUTO_INVALIDATION_ENA_SHIFT		6
#define			NO_AUTO					0
#define			ES_AUTO					1
#define			GS_AUTO					2
#define			ES_AND_GS_AUTO				3

#define	VGT_GS_VTX_REUSE			0x88d4

#define CC_GC_SHADER_PIPE_CFG			0x8950
#define		WR_DIS					BIT(0)
#define	GC_USER_SHADER_PIPE_CFG			0x8954
#define		INACTIVE_QD_PIPES_MASK			0x0000ff00
#define		INACTIVE_QD_PIPES_SHIFT			8
#define		INACTIVE_SIMDS_MASK			0x00ff0000
#define		INACTIVE_SIMDS_SHIFT			16

#define	VGT_INSTS_N				0x8974

#define	PA_CL_ENHANCE				0x8a14
#define		CLIP_VTX_REORDER_ENA			BIT(0)
#define		CLIP_SEQ_N_MASK				0xffffffff
#define		CLIP_SEQ_N_SHIFT			1

#define	PA_SU_LINE_STIPPLE_VALUE		0x8a60
#define	PA_SC_LINE_STIPPLE_STATE		0x8b10

#define	PA_SC_FORCE_EOV_MAX_CNTS		0x8b24
#define		FORCE_EOV_MAX_CLK_CNT_MASK		0xffffffff
#define		FORCE_EOV_MAX_CLK_CNT_SHIFT		0
#define		FORCE_EOV_MAX_REZ_CNT_MASK		0xffffffff
#define		FORCE_EOV_MAX_REZ_CNT_SHIFT		16

#define	PA_SC_FIFO_SZ				0x8bcc
#define		SC_PRIM_FIFO_SZ_MASK			0xffffffff
#define		SC_PRIM_FIFO_SZ_SHIFT			0
#define		SC_HIZ_TILE_FIFO_SZ_MASK		0xffffffff
#define		SC_HIZ_TILE_FIFO_SZ_SHIFT		12
#define		SC_EARLYZ_TILE_FIFO_SZ_MASK		0xffffffff
#define		SC_EARLYZ_TILE_FIFO_SZ_SHIFT		20

#define	SQ_CFG					0x8c00
#define		VC_ENA					BIT(0)
#define		EXPORT_SRC_C				BIT(1)
#define		CS_PRIO_MASK				0x000c0000
#define		CS_PRIO_SHIFT				18
#define		LS_PRIO_MASK				0x00300000
#define		LS_PRIO_SHIFT				20
#define		HS_PRIO_MASK				0x00c00000
#define		HS_PRIO_SHIFT				22
#define		PS_PRIO_MASK				0x03000000
#define		PS_PRIO_SHIFT				24
#define		VS_PRIO_MASK				0x0c000000
#define		VS_PRIO_SHIFT				26
#define		GS_PRIO_MASK				0x30000000
#define		GS_PRIO_SHIFT				28
#define		ES_PRIO_MASK				0xc0000000
#define		ES_PRIO_SHIFT				30

#define	SQ_GPR_RES_MGMT_0			0x8c04
#define		PS_GPRS_N_MASK				0xffffffff
#define		PS_GPRS_N_SHIFT				0
#define		VS_GPRS_N_MASK				0xffffffff
#define		VS_GPRS_N_SHIFT				16
#define		CLAUSE_TMP_GPRS_N_MASK			0xffffffff
#define		CLAUSE_TMP_GPRS_N_SHIFT			28

#define	SQ_GPR_RES_MGMT_1			0x8c08
#define		GS_GPRS_N_MASK				0xffffffff
#define		GS_GPRS_N_SHIFT				0
#define		ES_GPRS_N_MASK				0xffffffff
#define		ES_GPRS_N_SHIFT				16

#define	SQ_GPR_RES_MGMT_2			0x8c0c
#define		HS_GPRS_N_MASK				0xffffffff
#define		HS_GPRS_N_SHIFT				0
#define		LS_GPRS_N_MASK				0xffffffff
#define		LS_GPRS_N_SHIFT				16
#define SQ_GLOBAL_GPR_RES_MGMT_0		0x8c10
#define SQ_GLOBAL_GPR_RES_MGMT_1		0x8c14              
#define	SQ_THD_RES_MGMT_0			0x8c18
#define		PS_THDS_N_MASK				0xffffffff
#define		PS_THDS_N_SHIFT				0
#define		VS_THDS_N_MASK				0xffffffff
#define		VS_THDS_N_SHIFT				8
#define		GS_THDS_N_MASK				0xffffffff
#define		GS_THDS_N_SHIFT				16
#define		ES_THDS_N_MASK				0xffffffff
#define		ES_THDS_N_SHIFT				24

#define	SQ_THD_RES_MGMT_1			0x8c1c
#define		HS_THDS_N_MASK				0xffffffff
#define		HS_THDS_N_SHIFT				0
#define		LS_THDS_N_MASK				0xffffffff
#define		LS_THDS_N_SHIFT				8

#define	SQ_STACK_RES_MGMT_0			0x8c20
#define		PS_STACK_ENTRIES_N_MASK			0xffffffff
#define		PS_STACK_ENTRIES_N_SHIFT		0
#define		VS_STACK_ENTRIES_N_MASK			0xffffffff
#define		VS_STACK_ENTRIES_N_SHIFT		16

#define	SQ_STACK_RES_MGMT_1			0x8c24
#define		GS_STACK_ENTRIES_N_MASK			0xffffffff
#define		GS_STACK_ENTRIES_N_SHIFT		0
#define		ES_STACK_ENTRIES_N_MASK			0xffffffff
#define		ES_STACK_ENTRIES_N_SHIFT		16

#define	SQ_STACK_RES_MGMT_2			0x8c28
#define		HS_STACK_ENTRIES_N_MASK			0xffffffff
#define		HS_STACK_ENTRIES_N_SHIFT		0
#define		LS_STACK_ENTRIES_N_MASK			0xffffffff
#define		LS_STACK_ENTRIES_N_SHIFT		16

#define	SQ_MS_FIFO_SZS				0x8cf0
#define		CACHE_FIFO_SZ_MASK			0xffffffff
#define		CACHE_FIFO_SZ_SHIFT			0
#define		FETCH_FIFO_HIWATER_MASK			0xffffffff
#define		FETCH_FIFO_HIWATER_SHIFT		8
#define		DONE_FIFO_HIWATER_MASK			0xffffffff
#define		DONE_FIFO_HIWATER_SHIFT			16
#define		ALU_UPDATE_FIFO_HIWATER_MASK		0xffffffff
#define		ALU_UPDATE_FIFO_HIWATER_SHIFT		24

#define	SQ_DYN_GPR_CTL_PS_FLUSH_REQ 	   	0x8d8c

#define	SQ_LDS_RES_MGMT				0x8e2c

#define	SX_EXPORT_BUF_SZS			0x900c
#define		COLOR_BUF_SZ_MASK			0xffffffff
#define		COLOR_BUF_SZ_SHIFT			0
#define		POS_BUF_SZ_MASK				0xffffffff
#define		POS_BUF_SZ_SHIFT			8
#define		SMX_BUF_SZ_MASK				0xffffffff
#define		SMX_BUF_SZ_SHIFT			16

#define	SX_DEBUG_1				0x9058
#define		ENA_NEW_SMX_ADDR			BIT(16)

#define	SPI_CFG_CTL_0				0x9100
#define		GPR_WR_PRIO_MASK			0xffffffff
#define		GPR_WR_PRIO_SHIFT			0
#define	SPI_CFG_CTL_1				0x913c
#define		VTX_DONE_DELAY_MASK			0xffffffff
#define		VTX_DONE_DELAY_SHIFT			0
#define		INTERP_ONE_PRIM_PER_ROW			BIT(4)

#define	CGTS_TCC_DIS				0x9148
#define	CGTS_USER_TCC_DIS			0x914c

#define	TA_CTL_AUX				0x9508
#define		DIS_CUBE_WRAP				BIT(0)
#define		DIS_CUBE_ANISO				BIT(1)
#define		SYNC_GRADIENT				BIT(24)
#define		SYNC_WALKER				BIT(25)
#define		SYNC_ALIGNER				BIT(26)

#define	TCP_CHAN_STEER_LO			0x960c
#define	TCP_CHAN_STEER_HI			0x9610

#define CC_RB_BACKEND_DIS			0x98f4
#define		BACKEND_DIS_MASK			0xffffffff
#define		BACKEND_DIS_SHIFT			16

#define GB_ADDR_CFG				0x98f8
#define		PIPES_N_MASK				0x0000000f
#define		PIPES_N_SHIFT				0
#define		PIPE_INTERLEAVE_SZ_MASK			0xffffffff
#define		PIPE_INTERLEAVE_SZ_SHIFT		4
#define		BANK_INTERLEAVE_SZ_MASK			0xffffffff
#define		BANK_INTERLEAVE_SHIFT			8
#define		SES_N_MASK				0xffffffff
#define		SES_N_SHIFT				12
#define		SE_TILE_SZ_MASK				0xffffffff
#define		SE_TILE_SZ_SHIFT			16
#define		GPUS_N_MASK				0xffffffff
#define		GPUS_N_SHIFT				20
#define		MULTI_GPU_TILE_SZ_MASK			0xffffffff
#define		MULTI_GPU_TILE_SZ_SHIFT			24
#define		ROW_SZ_MASK				0x30000000
#define		ROW_SZ_SHIFT				28

#define GB_BACKEND_MAP  			0x98fc

#define CB_PERF_CTR_0_SEL_0			0x9a20
#define CB_PERF_CTR_0_SEL_1			0x9a24
#define CB_PERF_CTR_1_SEL_0			0x9a28
#define CB_PERF_CTR_1_SEL_1			0x9a2c
#define CB_PERF_CTR_2_SEL_0			0x9a30
#define CB_PERF_CTR_2_SEL_1			0x9a34
#define CB_PERF_CTR_3_SEL_0			0x9a38
#define CB_PERF_CTR_3_SEL_1			0x9a3c

#define	GC_USER_RB_BACKEND_DIS			0x9b7c

#define SMX_SAR_CTL_0				0xa008
#define	SMX_DC_CTL_0				0xa020
#define		USE_HASH_FUNC				BIT(0)
#define		SETS_N_MASK				0x000003fe
#define		SETS_N_SHIFT				1
#define		FLUSH_ALL_ON_EVT			BIT(10)
#define		STALL_ON_EVT				BIT(11)

#define	CP_RB_BASE				0xc100
#define	CP_RB_CTL				0xc104
#define		RB_BUF_LOG2_QWS_MASK			0xffffffff
#define		RB_BUF_LOG2_QWS_SHIFT			0
#define		RB_BLK_LOG2_QWS_MASK			0xffffffff
#define		RB_BLK_LOG2_QWS_SHIFT			8
#define		RB_NO_UPDATE				BIT(27)
#define		RB_RPTR_WR_ENA				BIT(31)
#define		BUF_SWAP_32BIT				BIT(16)

#define	CP_RB_RPTR_WR				0xc108
#define	CP_RB_RPTR_ADDR				0xc10c
#define		RB_RPTR_SWAP_MASK			0xffffffff
#define		RB_RPTR_SWAP_SHIFT			0
#define	CP_RB_RPTR_ADDR_HI			0xc110
#define	CP_RB_WPTR				0xc114

#define CP_INT_CTL				0xc124
#define		CNTX_BUSY_INT_ENA			BIT(19)
#define		CNTX_EMPTY_INT_ENA			BIT(20)
#define		SCRATCH_INT_ENA				BIT(25)
#define		TIME_STAMP_INT_ENA			BIT(26)
#define		IB2_INT_ENA				BIT(29)
#define		IB1_INT_ENA				BIT(30)
#define		RB_INT_ENA				BIT(31)
#define CP_INT_STATUS				0xc128
#define		SCRATCH_INT_STAT			BIT(25)
#define		TIME_STAMP_INT_STAT			BIT(26)
#define		IB2_INT_STAT				BIT(29)
#define		IB1_INT_STAT				BIT(30)

#define	CP_PFP_UCODE_ADDR			0xc150
#define	CP_PFP_UCODE_DATA			0xc154
#define		RB_INT_STAT				BIT(31)

#define	CP_ME_RAM_RADDR				0xc158
#define	CP_ME_RAM_WADDR				0xc15C
#define	CP_ME_RAM_DATA				0xc160

#define	CP_DEBUG				0xc1fc

/* start of context register area: 0x28000-0x29000 */
/* from there we must use indirect MMIO because above reg MMIO size */
#define DB_RENDER_CTL				0x28000
#define DB_CNT_CTL				0x28004
#define DB_DEPTH_VIEW				0x28008
#define		SLICE_MAX_MASK				0x00ffe000
#define		SLICE_MAX_SHIFT				13
#define DB_RENDER_OVERRIDE_0			0x2800c
#define DB_RENDER_OVERRIDE_1			0x28010
#define DB_HTILE_DATA_BASE			0x28014

#define DB_STENCIL_CLR				0x28028
#define DB_DEPTH_CLR				0x2802c
#define PA_SC_SCR_SCISSOR_TL			0x28030
#define PA_SC_SCR_SCISSOR_BR			0x28034

#define DB_Z_INFO				0x28040
#define		Z_ARRAY_MODE_MASK			0xffffffff
#define		Z_ARRAY_MODE_SHIFT			4
#define		DB_TILE_SPLIT_MASK			0x00000700
#define		DB_TILE_SPLIT_SHIFT			8
#define		DB_BANKS_N_MASK				0x00007000
#define		DB_BANKS_N_SHIFT			12
#define		DB_BANK_W_MASK				0x00070000
#define		DB_BANK_W_SHIFT				16
#define		DB_BANK_H_MASK				0x00700000
#define		DB_BANK_H_SHIFT				20
#define		DB_MACRO_TILE_ASPECT_MASK		0x07000000
#define		DB_MACRO_TILE_ASPECT_SHIFT		24

#define DB_STENCIL_INFO				0x28044
#define		DB_FMT					BIT(0)
#define		TILE_SPLIT_MASK				0x00000700
#define		TILE_SPLIT_SHIFT			8

#define SQ_ALU_CONST_BUF_SZ_PS_0		0x28140
#define SQ_ALU_CONST_BUF_SZ_PS_1		0x28144
#define SQ_ALU_CONST_BUF_SZ_PS_2		0x28148
#define SQ_ALU_CONST_BUF_SZ_PS_3		0x2814c
#define SQ_ALU_CONST_BUF_SZ_PS_4		0x28150
#define SQ_ALU_CONST_BUF_SZ_PS_5		0x28154
#define SQ_ALU_CONST_BUF_SZ_PS_6		0x28158
#define SQ_ALU_CONST_BUF_SZ_PS_7		0x2815c
#define SQ_ALU_CONST_BUF_SZ_PS_8		0x28160
#define SQ_ALU_CONST_BUF_SZ_PS_9		0x28164
#define SQ_ALU_CONST_BUF_SZ_PS_A		0x28168
#define SQ_ALU_CONST_BUF_SZ_PS_B		0x2816c
#define SQ_ALU_CONST_BUF_SZ_PS_C		0x28170
#define SQ_ALU_CONST_BUF_SZ_PS_D		0x28174
#define SQ_ALU_CONST_BUF_SZ_PS_E		0x28178
#define SQ_ALU_CONST_BUF_SZ_PS_F		0x2817c
#define SQ_ALU_CONST_BUF_SZ_VS_0		0x28180
#define SQ_ALU_CONST_BUF_SZ_VS_1		0x28184
#define SQ_ALU_CONST_BUF_SZ_VS_2		0x28188
#define SQ_ALU_CONST_BUF_SZ_VS_3		0x2818c
#define SQ_ALU_CONST_BUF_SZ_VS_4		0x28190
#define SQ_ALU_CONST_BUF_SZ_VS_5		0x28194
#define SQ_ALU_CONST_BUF_SZ_VS_6		0x28198
#define SQ_ALU_CONST_BUF_SZ_VS_7		0x2819c
#define SQ_ALU_CONST_BUF_SZ_VS_8		0x281a0
#define SQ_ALU_CONST_BUF_SZ_VS_9		0x281a4
#define SQ_ALU_CONST_BUF_SZ_VS_A		0x281a8
#define SQ_ALU_CONST_BUF_SZ_VS_B		0x281ac
#define SQ_ALU_CONST_BUF_SZ_VS_C		0x281b0
#define SQ_ALU_CONST_BUF_SZ_VS_D		0x281b4
#define SQ_ALU_CONST_BUF_SZ_VS_E		0x281b8
#define SQ_ALU_CONST_BUF_SZ_VS_F		0x281bc
#define SQ_ALU_CONST_BUF_SZ_GS_0		0x281c0
#define SQ_ALU_CONST_BUF_SZ_GS_1		0x281c4
#define SQ_ALU_CONST_BUF_SZ_GS_2		0x281c8
#define SQ_ALU_CONST_BUF_SZ_GS_3		0x281cc
#define SQ_ALU_CONST_BUF_SZ_GS_4		0x281d0
#define SQ_ALU_CONST_BUF_SZ_GS_5		0x281d4
#define SQ_ALU_CONST_BUF_SZ_GS_6		0x281d8
#define SQ_ALU_CONST_BUF_SZ_GS_7		0x281dc
#define SQ_ALU_CONST_BUF_SZ_GS_8		0x281e0
#define SQ_ALU_CONST_BUF_SZ_GS_9		0x281e4 
#define SQ_ALU_CONST_BUF_SZ_GS_A		0x281e8
#define SQ_ALU_CONST_BUF_SZ_GS_B		0x281ec
#define SQ_ALU_CONST_BUF_SZ_GS_C		0x281f0
#define SQ_ALU_CONST_BUF_SZ_GS_D		0x281f4
#define SQ_ALU_CONST_BUF_SZ_GS_E		0x281f8
#define SQ_ALU_CONST_BUF_SZ_GS_F		0x281fc
#define PA_SC_WND_OF				0x28200
#define PA_SC_WND_SCISSOR_TL			0x28204
#define PA_SC_WND_SCISSOR_BR			0x28208
#define PA_SC_CLIPRECT_RULE			0x2820c
#define PA_SC_CLIPRECT_0_TL			0x28210
#define PA_SC_CLIPRECT_0_BR			0x28214
#define PA_SC_CLIPRECT_1_TL			0x28218
#define PA_SC_CLIPRECT_1_BR			0x2821c
#define PA_SC_CLIPRECT_2_TL			0x28220
#define PA_SC_CLIPRECT_2_BR			0x28224
#define PA_SC_CLIPRECT_3_TL			0x28228
#define PA_SC_CLIPRECT_3_BR			0x2822c
#define PA_SC_EDGERULE				0x28230
#define PA_SU_HW_SCR_OF				0x28234
#define CB_TGT_MASK				0x28238
#define CB_SHADER_MASK				0x2823c
#define PA_SC_GENERIC_SCISSOR_TL		0x28240
#define PA_SC_GENERIC_SCISSOR_BR		0x28244

#define PA_SC_VPORT_SCISSOR_0_TL		0x28250
#define PA_SC_VPORT_SCISSOR_0_BR		0x28254
#define PA_SC_VPORT_SCISSOR_1_TL		0x28258
#define PA_SC_VPORT_SCISSOR_1_BR		0x2825c
#define PA_SC_VPORT_SCISSOR_2_TL		0x28260
#define PA_SC_VPORT_SCISSOR_2_BR		0x28264
#define PA_SC_VPORT_SCISSOR_3_TL		0x28268
#define PA_SC_VPORT_SCISSOR_3_BR		0x2826c
#define PA_SC_VPORT_SCISSOR_4_TL		0x28270
#define PA_SC_VPORT_SCISSOR_4_BR		0x28274
#define PA_SC_VPORT_SCISSOR_5_TL		0x28278
#define PA_SC_VPORT_SCISSOR_5_BR		0x2827c
#define PA_SC_VPORT_SCISSOR_6_TL		0x28280
#define PA_SC_VPORT_SCISSOR_6_BR		0x28284
#define PA_SC_VPORT_SCISSOR_7_TL		0x28288
#define PA_SC_VPORT_SCISSOR_7_BR		0x2828c
#define PA_SC_VPORT_SCISSOR_8_TL		0x28290
#define PA_SC_VPORT_SCISSOR_8_BR		0x28294
#define PA_SC_VPORT_SCISSOR_9_TL		0x28298
#define PA_SC_VPORT_SCISSOR_9_BR		0x2829c
#define PA_SC_VPORT_SCISSOR_A_TL		0x282a0
#define PA_SC_VPORT_SCISSOR_A_BR		0x282a4
#define PA_SC_VPORT_SCISSOR_B_TL		0x282a8
#define PA_SC_VPORT_SCISSOR_B_BR		0x282ac
#define PA_SC_VPORT_SCISSOR_C_TL		0x282b0
#define PA_SC_VPORT_SCISSOR_C_BR		0x282b4
#define PA_SC_VPORT_SCISSOR_D_TL		0x282b8
#define PA_SC_VPORT_SCISSOR_D_BR		0x282bc
#define PA_SC_VPORT_SCISSOR_E_TL		0x282c0
#define PA_SC_VPORT_SCISSOR_E_BR		0x282c4
#define PA_SC_VPORT_SCISSOR_F_TL		0x282c8
#define PA_SC_VPORT_SCISSOR_F_BR		0x282cc
#define PA_SC_VPORT_ZMIN_0			0x282d0
#define PA_SC_VPORT_ZMAX_0			0x282d4
#define PA_SC_VPORT_ZMIN_1			0x282d8
#define PA_SC_VPORT_ZMAX_1			0x282dc
#define PA_SC_VPORT_ZMIN_2			0x282e0
#define PA_SC_VPORT_ZMAX_2			0x282e4
#define PA_SC_VPORT_ZMIN_3			0x282e8
#define PA_SC_VPORT_ZMAX_3			0x282ec
#define PA_SC_VPORT_ZMIN_4			0x282f0
#define PA_SC_VPORT_ZMAX_4			0x282f4
#define PA_SC_VPORT_ZMIN_5			0x282f8
#define PA_SC_VPORT_ZMAX_5			0x282fc
#define PA_SC_VPORT_ZMIN_6			0x28300
#define PA_SC_VPORT_ZMAX_6			0x28304
#define PA_SC_VPORT_ZMIN_7			0x28308
#define PA_SC_VPORT_ZMAX_7			0x2830c
#define PA_SC_VPORT_ZMIN_8			0x28310
#define PA_SC_VPORT_ZMAX_8			0x28314
#define PA_SC_VPORT_ZMIN_9			0x28318
#define PA_SC_VPORT_ZMAX_9			0x2831c
#define PA_SC_VPORT_ZMIN_A			0x28320
#define PA_SC_VPORT_ZMAX_A			0x28324
#define PA_SC_VPORT_ZMIN_B			0x28328
#define PA_SC_VPORT_ZMAX_B			0x2832c
#define PA_SC_VPORT_ZMIN_C			0x28330
#define PA_SC_VPORT_ZMAX_C			0x28334
#define PA_SC_VPORT_ZMIN_D			0x28338
#define PA_SC_VPORT_ZMAX_D			0x2833c
#define PA_SC_VPORT_ZMIN_E			0x28340
#define PA_SC_VPORT_ZMAX_E			0x28344
#define PA_SC_VPORT_ZMIN_F			0x28348
#define PA_SC_VPORT_ZMAX_F			0x2834c
#define SX_MISC					0x28350
#define SX_SURF_SYNC				0x28354

#define SQ_VTX_SEMANTIC_00			0x28380
#define SQ_VTX_SEMANTIC_01			0x28384
#define SQ_VTX_SEMANTIC_02			0x28388
#define SQ_VTX_SEMANTIC_03			0x2838c
#define SQ_VTX_SEMANTIC_04			0x28390
#define SQ_VTX_SEMANTIC_05			0x28394
#define SQ_VTX_SEMANTIC_06			0x28398
#define SQ_VTX_SEMANTIC_07			0x2839c
#define SQ_VTX_SEMANTIC_08			0x283a0
#define SQ_VTX_SEMANTIC_09			0x283a4
#define SQ_VTX_SEMANTIC_0A			0x283a8
#define SQ_VTX_SEMANTIC_0B			0x283ac
#define SQ_VTX_SEMANTIC_0C			0x283b0
#define SQ_VTX_SEMANTIC_0D			0x283b4
#define SQ_VTX_SEMANTIC_0E			0x283b8
#define SQ_VTX_SEMANTIC_0F			0x283bc
#define SQ_VTX_SEMANTIC_10			0x283c0
#define SQ_VTX_SEMANTIC_11			0x283c4
#define SQ_VTX_SEMANTIC_12			0x283c8
#define SQ_VTX_SEMANTIC_13			0x283cc
#define SQ_VTX_SEMANTIC_14			0x283d0
#define SQ_VTX_SEMANTIC_15			0x283d4
#define SQ_VTX_SEMANTIC_16			0x283d8
#define SQ_VTX_SEMANTIC_17			0x283dc
#define SQ_VTX_SEMANTIC_18			0x283e0
#define SQ_VTX_SEMANTIC_19			0x283e4
#define SQ_VTX_SEMANTIC_1A			0x283e8
#define SQ_VTX_SEMANTIC_1B			0x283ec
#define SQ_VTX_SEMANTIC_1C			0x283f0
#define SQ_VTX_SEMANTIC_1D			0x283f4
#define SQ_VTX_SEMANTIC_1E			0x283f8
#define SQ_VTX_SEMANTIC_1F			0x283fc
#define VGT_MAX_VTX_IDX				0x28400
#define VGT_MIN_VTX_IDX				0x28404
#define VGT_IDX_OF				0x28408
#define VGT_MULTI_PRIM_IB_RESET_IDX		0x2840c
#define SX_ALPHA_TEST_CTL			0x28410
#define CB_BLEND_RED				0x28414
#define CB_BLEND_GREEN				0x28418
#define CB_BLEND_BLUE				0x2841c
#define CB_BLEND_ALPHA				0x28420

#define DB_STENCILREFMASK			0x28430
#define DB_STENCILREFMASK_BF			0x28434
#define SX_ALPHA_REF				0x28438
#define PA_CL_VPORT_X_SCALE_0			0x2843c
#define PA_CL_VPORT_X_OF_0			0x28440
#define PA_CL_VPORT_Y_SCALE_0			0x28444
#define PA_CL_VPORT_Y_OF_0			0x28448
#define PA_CL_VPORT_ZSCALE_0			0x2844c
#define PA_CL_VPORT_Z_OF_0			0x28450
#define PA_CL_VPORT_X_SCALE_1			0x28454
#define PA_CL_VPORT_X_OF_1			0x28458
#define PA_CL_VPORT_Y_SCALE_1			0x2845c
#define PA_CL_VPORT_Y_OF_1			0x28460
#define PA_CL_VPORT_Z_SCALE_1			0x28464
#define PA_CL_VPORT_Z_OF_1			0x28468
#define PA_CL_VPORT_X_SCALE_2			0x2846c
#define PA_CL_VPORT_X_OF_2			0x28470
#define PA_CL_VPORT_Y_SCALE_2			0x28474
#define PA_CL_VPORT_Y_OF_2			0x28478
#define PA_CL_VPORT_Z_SCALE_2			0x2847c
#define PA_CL_VPORT_Z_OF_2			0x28480
#define PA_CL_VPORT_X_SCALE_3			0x28484
#define PA_CL_VPORT_X_OF_3			0x28488
#define PA_CL_VPORT_Y_SCALE_3			0x2848c
#define PA_CL_VPORT_Y_OF_3			0x28490
#define PA_CL_VPORT_Z_SCALE_3			0x28494
#define PA_CL_VPORT_Z_OF_3			0x28498
#define PA_CL_VPORT_X_SCALE_4			0x2849c
#define PA_CL_VPORT_X_OF_4			0x284a0
#define PA_CL_VPORT_Y_SCALE_4			0x284a4
#define PA_CL_VPORT_Y_OF_4			0x284a8
#define PA_CL_VPORT_Z_SCALE_4			0x284ac
#define PA_CL_VPORT_Z_OF_4			0x284b0
#define PA_CL_VPORT_X_SCALE_5			0x284b4
#define PA_CL_VPORT_X_OF_5			0x284b8
#define PA_CL_VPORT_Y_SCALE_5			0x284bc
#define PA_CL_VPORT_Y_OF_5			0x284c0
#define PA_CL_VPORT_Z_SCALE_5			0x284c4
#define PA_CL_VPORT_Z_OF_5			0x284c8
#define PA_CL_VPORT_X_SCALE_6			0x284cc
#define PA_CL_VPORT_X_OF_6			0x284d0
#define PA_CL_VPORT_Y_SCALE_6			0x284d4
#define PA_CL_VPORT_Y_OF_6			0x284d8
#define PA_CL_VPORT_Z_SCALE_6			0x284dc
#define PA_CL_VPORT_Z_OF_6			0x284e0
#define PA_CL_VPORT_X_SCALE_7			0x284e4
#define PA_CL_VPORT_X_OF_7			0x284e8
#define PA_CL_VPORT_Y_SCALE_7			0x284ec
#define PA_CL_VPORT_Y_OF_7			0x284f0
#define PA_CL_VPORT_Z_SCALE_7			0x284f4
#define PA_CL_VPORT_Z_OF_7			0x284f8
#define PA_CL_VPORT_X_SCALE_8			0x284fc
#define PA_CL_VPORT_X_OF_8			0x28500
#define PA_CL_VPORT_Y_SCALE_8			0x28504
#define PA_CL_VPORT_Y_OF_8			0x28508
#define PA_CL_VPORT_Z_SCALE_8			0x2850c
#define PA_CL_VPORT_Z_OF_8			0x28510
#define PA_CL_VPORT_X_SCALE_9			0x28514
#define PA_CL_VPORT_X_OF_9			0x28518
#define PA_CL_VPORT_Y_SCALE_9			0x2851c
#define PA_CL_VPORT_Y_OF_9			0x28520
#define PA_CL_VPORT_Z_SCALE_9			0x28524
#define PA_CL_VPORT_Z_OF_9			0x28528
#define PA_CL_VPORT_X_SCALE_A			0x2852c
#define PA_CL_VPORT_X_OF_A			0x28530
#define PA_CL_VPORT_Y_SCALE_A			0x28534
#define PA_CL_VPORT_Y_OF_A			0x28538
#define PA_CL_VPORT_Z_SCALE_A			0x2853c
#define PA_CL_VPORT_Z_OF_A			0x28540
#define PA_CL_VPORT_X_SCALE_B			0x28544
#define PA_CL_VPORT_X_OF_B			0x28548
#define PA_CL_VPORT_Y_SCALE_B			0x2854c
#define PA_CL_VPORT_Y_OF_B			0x28550
#define PA_CL_VPORT_Z_SCALE_B			0x28554
#define PA_CL_VPORT_Z_OF_B			0x28558
#define PA_CL_VPORT_X_SCALE_C			0x2855c
#define PA_CL_VPORT_X_OF_C			0x28560
#define PA_CL_VPORT_Y_SCALE_C			0x28564
#define PA_CL_VPORT_Y_OF_C			0x28568
#define PA_CL_VPORT_Z_SCALE_C			0x2856c
#define PA_CL_VPORT_Z_OF_C			0x28570
#define PA_CL_VPORT_X_SCALE_D			0x28574
#define PA_CL_VPORT_X_OF_D			0x28578
#define PA_CL_VPORT_Y_SCALE_D			0x2857c
#define PA_CL_VPORT_Y_OF_D			0x28580
#define PA_CL_VPORT_Z_SCALE_D			0x28584
#define PA_CL_VPORT_Z_OF_D			0x28588
#define PA_CL_VPORT_X_SCALE_E			0x2858c
#define PA_CL_VPORT_X_OF_E			0x28590
#define PA_CL_VPORT_Y_SCALE_E			0x28594
#define PA_CL_VPORT_Y_OF_E			0x28598
#define PA_CL_VPORT_Z_SCALE_E			0x2859c
#define PA_CL_VPORT_Z_OF_E			0x285a0
#define PA_CL_VPORT_X_SCALE_F			0x285a4
#define PA_CL_VPORT_X_OF_F			0x285a8
#define PA_CL_VPORT_Y_SCALE_F			0x285ac
#define PA_CL_VPORT_Y_OF_F			0x285b0
#define PA_CL_VPORT_Z_SCALE_F			0x285b4
#define PA_CL_VPORT_Z_OF_F			0x285b8
#define PA_CL_UCP_0_X				0x285bc
#define PA_CL_UCP_0_Y				0x285c0
#define PA_CL_UCP_0_Z				0x285c4
#define PA_CL_UCP_0_W				0x285c8
#define PA_CL_UCP_1_X				0x285cc
#define PA_CL_UCP_1_Y				0x285d0
#define PA_CL_UCP_1_Z				0x285d4
#define PA_CL_UCP_1_W				0x285d8
#define PA_CL_UCP_2_X				0x285dc
#define PA_CL_UCP_2_Y				0x285e0
#define PA_CL_UCP_2_Z				0x285e4
#define PA_CL_UCP_2_W				0x285e8
#define PA_CL_UCP_3_X				0x285ec
#define PA_CL_UCP_3_Y				0x285f0
#define PA_CL_UCP_3_Z				0x285f4
#define PA_CL_UCP_3_W				0x285f8
#define PA_CL_UCP_4_X				0x285fc
#define PA_CL_UCP_4_Y				0x28600
#define PA_CL_UCP_4_Z				0x28604
#define PA_CL_UCP_4_W				0x28608
#define PA_CL_UCP_5_X				0x2860c
#define PA_CL_UCP_5_Y				0x28610
#define PA_CL_UCP_5_Z				0x28614
#define PA_CL_UCP_5_W				0x28618
#define SPI_VS_OUT_ID_0				0x2861c
#define SPI_VS_OUT_ID_1				0x28620
#define	SPI_VS_OUT_ID_2				0x28624
#define	SPI_VS_OUT_ID_3				0x28628
#define	SPI_VS_OUT_ID_4				0x2862c
#define	SPI_VS_OUT_ID_5				0x28630
#define	SPI_VS_OUT_ID_6				0x28634
#define	SPI_VS_OUT_ID_7				0x28638
#define	SPI_VS_OUT_ID_8				0x2863c
#define	SPI_VS_OUT_ID_9				0x28640
#define SPI_PS_INPUT_CTL_00			0x28644
#define SPI_PS_INPUT_CTL_01			0x28648
#define SPI_PS_INPUT_CTL_02			0x2864c
#define SPI_PS_INPUT_CTL_03			0x28650
#define SPI_PS_INPUT_CTL_04			0x28654
#define SPI_PS_INPUT_CTL_05			0x28658
#define SPI_PS_INPUT_CTL_06			0x2865c
#define SPI_PS_INPUT_CTL_07			0x28660
#define SPI_PS_INPUT_CTL_08			0x28664
#define SPI_PS_INPUT_CTL_09			0x28668
#define SPI_PS_INPUT_CTL_0A			0x2866c
#define SPI_PS_INPUT_CTL_0B			0x28670
#define SPI_PS_INPUT_CTL_0C			0x28674
#define SPI_PS_INPUT_CTL_0D			0x28678
#define SPI_PS_INPUT_CTL_0E			0x2867c
#define SPI_PS_INPUT_CTL_0F			0x28680
#define SPI_PS_INPUT_CTL_10			0x28684
#define SPI_PS_INPUT_CTL_11			0x28688
#define SPI_PS_INPUT_CTL_12			0x2868c
#define SPI_PS_INPUT_CTL_13			0x28690
#define SPI_PS_INPUT_CTL_14			0x28694
#define SPI_PS_INPUT_CTL_15			0x28698
#define SPI_PS_INPUT_CTL_16			0x2869c
#define SPI_PS_INPUT_CTL_17			0x286a0
#define SPI_PS_INPUT_CTL_18			0x286a4
#define SPI_PS_INPUT_CTL_19			0x286a8
#define SPI_PS_INPUT_CTL_1A			0x286ac
#define SPI_PS_INPUT_CTL_1B			0x286b0
#define SPI_PS_INPUT_CTL_1C			0x286b4
#define SPI_PS_INPUT_CTL_1D			0x286b8
#define SPI_PS_INPUT_CTL_1E			0x286bc
#define SPI_PS_INPUT_CTL_1F			0x286c0
#define SPI_VS_OUT_CFG				0x286c4
#define SPI_THD_GROUPING			0x286c8
#define	SPI_PS_IN_CTL_0				0x286cc
#define		INTERP_N_MASK				0xffffffff
#define		INTERP_N_SHIFT				0
#define		POS					BIT(8)
#define		POS_CENTROID				BIT(9)
#define		POS_ADDR_MASK				0xffffffff
#define		POS_ADDR_SHIFT				10
#define		PARAM_GEN_MASK				0xffffffff
#define		PARAM_GEN_SHIFT				15
#define		PARAM_GEN_ADDR_MASK			0xffffffff
#define		PARAM_GEN_ADDR_SHIFT			19
#define		BARYC_SAMPLE_CTL_MASK			0xffffffff
#define		BARYC_SAMPLE_CTL_SHIFT			26
#define		PERSP_GRADIENT_ENA			BIT(28)
#define		LINEAR_GRADIENT_ENA			BIT(29)
#define		POS_SAMPLE				BIT(30)
#define		BARYC_AT_SAMPLE_ENA			BIT(31)
#define SPI_PS_IN_CTL_1				0x286d0
#define SPI_INTERP_CTL_0			0x286d4
#define SPI_INPUT_Z				0x286d8
#define SPI_FOG_CTL				0x286dc
#define SPI_BARYC_CTL				0x286e0
#define SPI_PS_IN_CTL_2				0x286e4
#define SPI_COMPUTE_INPUT_CT			0x286e8
#define SPI_COMPUTE_THDS_N_X			0x286ec
#define SPI_COMPUTE_THDS_N_Y			0x286f0
#define SPI_COMPUTE_THDS_N_Z			0x286f4

#define GDS_ADDR_BASE				0x28720
#define GDS_ADDR_SZ				0x28724
#define GDS_ORDERED_WAVE_PER_SE			0x28728

#define CB_BLEND_0_CTL				0x28780
#define CB_BLEND_1_CTL				0x28784
#define CB_BLEND_2_CTL				0x28788
#define CB_BLEND_3_CTL				0x2878c
#define CB_BLEND_4_CTL				0x28790
#define CB_BLEND_5_CTL				0x28794
#define CB_BLEND_6_CTL				0x28798
#define CB_BLEND_7_CTL				0x2879c

#define CS_COPY_STATE				0x287cc

#define GFX_COPY_STATE				0x287d0
#define PA_CL_POINT_X_RAD			0x287d4
#define PA_CL_POINT_Y_RAD			0x287d8
#define PA_CL_POINT_SZ				0x287dc
#define PA_CL_POINT_CULL_RAD			0x287e0

#define DB_DEPTH_CTL				0x28800
#define		STENCIL_ENA				BIT(0)
#define		Z_ENA					BIT(1)
#define		Z_WRITE_ENA				BIT(2)
#define		ZFUNC_MASK				0x00000070			
#define		ZFUNC_SHIFT				4		
#define		BACKFACE_ENA				BIT(7)
#define		STENCILFUNC_MASK			0x00000700
#define		STENCILFUNC_SHIFT			8
#define			STENCILFUNC_NEVER			0
#define			STENCILFUNC_LESS			1
#define			STENCILFUNC_EQUAL			2
#define			STENCILFUNC_LEQUAL			3
#define			STENCILFUNC_GREATER			4
#define			STENCILFUNC_NOTEQUAL			5
#define			STENCILFUNC_GEQUAL			6
#define			STENCILFUNC_ALWAYS			7
#define		STENCILFAIL_MASK			0x00003800
#define		STENCILFAIL_SHIFT			11
#define			STENCILFAIL_KEEP			0
#define			STENCILFAIL_ZERO			1
#define			STENCILFAIL_REPLACE			2
#define			STENCILFAIL_INCR			3
#define			STENCILFAIL_DECR			4
#define			STENCILFAIL_INVERT			5
#define			STENCILFAIL_INCR_WRAP			6
#define			STENCILFAIL_DECR_WRAP			7
#define		STENCILZPASS_MASK			0x001c0000
#define		STENCILZPASS_SHIFT			14
#define		STENCILZFAIL_MASK			0x000e0000
#define		STENCILZFAIL_SHIFT			17
#define		STENCILFUNC_BF_MASK			0x00700000
#define		STENCILFUNC_BF_SHIFT			20
#define		STENCILFAIL_BF_MASK			0x03800000
#define		STENCILFAIL_BF_SHIFT			23
#define		STENCILZPASS_BF_MASK			0x1c000000
#define		STENCILZPASS_BF_SHIFT			26
#define		STENCILZFAIL_BF_MASK			0xe0000000
#define		STENCILZFAIL_BF_SHIFT			29

#define CB_COLOR_CTL				0x28808
#define DB_SHADER_CTL				0x2880c
#define PA_CL_CLIP_CTL				0x28810
#define PA_SU_SC_MODE_CTL			0x28814
#define PA_CL_VTE_CTL				0x28818
#define PA_CL_VS_OUT_CTL			0x2881c
#define PA_CL_NANINF_CTL			0x28820
#define PA_SU_LINE_STIPPLE_CTL			0x28824
#define PA_SU_LINE_STIPPLE_SCALE		0x28828
#define PA_SU_PRIM_FILTER_CTL			0x2882c
#define SQ_LSTMP_RING_ITEM_SZ			0x28830
#define SQ_HSTMP_RING_ITEM_SZ			0x28834
#define SQ_DYN_GPR_RES_LIMIT_1			0x28838

#define SQ_PGM_START_PS				0x28840
#define SQ_PGM_RES_PS				0x28844
#define SQ_PGM_RES_2_PS				0x28848
#define SQ_PGM_EXPORTS_PS			0x2884c

#define SQ_PGM_START_VS				0x2885c
#define SQ_PGM_RES_VS				0x28860
#define SQ_PGM_RES_2_VS				0x28864

#define SQ_PGM_START_GS				0x28874
#define SQ_PGM_RES_GS				0x28878
#define SQ_PGM_RES_2_GS				0x2887c

#define SQ_PGM_START_ES				0x2888c
#define SQ_PGM_RES_ES				0x28890
#define SQ_PGM_RES_2_ES				0x28894

#define SQ_PGM_START_FS				0x288a4
#define SQ_PGM_START_FS				0x288a4
#define SQ_PGM_RES_FS				0x288a8

#define SQ_PGM_START_HS				0x288b8
#define SQ_PGM_RES_HS				0x288bc
#define SQ_PGM_RES_2_HS				0x288c0

#define SQ_PGM_START_LS				0x288d0
#define SQ_PGM_RES_LS				0x288d4
#define SQ_PGM_RES_2_LS				0x288d8

#define SQ_LDS_ALLOC				0x288e8
#define SQ_LDS_ALLOC_PS				0x288ec
#define SQ_VTX_SEMANTIC_CLR			0x288f0

#define SQ_ESGS_RING_ITEM_SZ			0x28900
#define SQ_GSVS_RING_ITEM_SZ			0x28904
#define SQ_ESTMP_RING_ITEM_SZ			0x28908
#define SQ_GSTMP_RING_ITEM_SZ			0x2890c
#define SQ_VSTMP_RING_ITEM_SZ			0x28910
#define SQ_PSTMP_RING_ITEM_SZ			0x28914

#define SQ_GS_VERT_ITEM_SZ_0			0x2891c
#define SQ_GS_VERT_ITEM_SZ_1			0x28920
#define SQ_GS_VERT_ITEM_SZ_2			0x28924
#define SQ_GS_VERT_ITEM_SZ_3			0x28928

#define PA_SU_POINT_SZ				0x28a00
#define PA_SU_POINT_MINMAX			0x28a04
#define PA_SU_LINE_CTL				0x28a08
#define PA_SC_LINE_STIPPLE			0x28a0c
#define VGT_OUTPUT_PATH_CTL			0x28a10
#define VGT_HOS_CTL				0x28a14
#define VGT_HOS_MAX_TESS_LVL			0x28a18
#define VGT_HOS_MIN_TESS_LVL			0x28a1c
#define VGT_HOS_REUSE_DEPTH			0x28a20
#define VGT_GROUP_PRIM_TYPE			0x28a24
#define VGT_GROUP_FIRST_DECR			0x28a28
#define VGT_GROUP_DECR				0x28a2c
#define VGT_GROUP_VECT_0_CTL			0x28a30
#define VGT_GROUP_VECT_1_CTL			0x28a34
#define VGT_GROUP_VECT_0_FMT_CTL		0x28a38
#define VGT_GROUP_VECT_1_FMT_CTL		0x28a3c
#define VGT_GS_MODE				0x28a40

#define PA_SC_MODE_CTL_0			0x28a48
#define PA_SC_MODE_CTL_1			0x28a4c
#define VGT_ENHANCE				0x28a50
#define VGT_GS_PER_ES				0x28a54
#define VGT_ES_PER_GS				0x28a58
#define VGT_GS_PER_VS				0x28a5c

#define VGT_GS_OUT_PRIM_TYPE			0x28a6c

#define VGT_PRIM_ID_ENA				0x28a84

#define VGT_MULTI_PRIM_IB_RESET_ENA		0x28a94

#define VGT_INST_STEP_RATE_0			0x28aa0
#define VGT_INST_STEP_RATE_1			0x28aa4

#define VGT_REUSE_OFF				0x28ab4
#define VGT_VTX_CNT_ENA				0x28ab8

#define DB_SRESULTS_CMP_STATE_0			0x28ac0
#define DB_SRESULTS_CMP_STATE_1			0x28ac4
#define DB_PRELOAD_CTL				0x28ac8

#define VGT_STRMOUT_VTX_STRIDE_0		0x28ad4

#define VGT_STRMOUT_VTX_STRIDE_1		0x28ae4

#define VGT_STRMOUT_VTX_STRIDE_2		0x28af4

#define VGT_STRMOUT_VTX_STRIDE_3		0x28b04

#define VGT_STRMOUT_DRAW_OPAQUE_OF		0x28b28
#define VGT_STRMOUT_DRAW_OPAQUE_BUF_FILLED_SZ	0x28b2c
#define VGT_STRMOUT_DRAW_OPAQUE_VTX_STRIDE	0x28b30

#define VGT_GS_MAX_VERT_OUT			0x28b38

#define VGT_SHADER_STAGES_ENA			0x28b54
#define VGT_LS_HS_CFG				0x28b58
#define VGT_LS_SZ				0x28b5c
#define VGT_HS_SZ				0x28b60
#define VGT_LS_HS_ALLOC				0x28b64
#define VGT_HS_PATCH_CONST			0x28b68
#define VGT_TF_PARAM				0x28b6c
#define DB_ALPHA_TO_MASK			0x28b70
#define VGT_GS_INST_CNT				0x28b74
#define VGT_DISPATCH_INITIATOR			0x28b74/* 2 names */
#define PA_SU_POLY_OF_DB_FMT_CTL		0x28b78
#define PA_SU_POLY_OF_CLAMP			0x28b7c
#define PA_SU_POLY_OF_FRONT_SCALE		0x28b80
#define PA_SU_POLY_OF_FRONT_OF			0x28b84
#define PA_SU_POLY_OF_BACK_SCALE		0x28b88
#define PA_SU_POLY_OF_BACK_OF			0x28b8c

#define VGT_STRMOUT_CFG				0x28b94
#define VGT_STRMOUT_BUF_CFG			0x28b98

#define PA_SC_LINE_CTL				0x28c00
#define PA_SC_AA_CFG				0x28c04
#define		MSAA_SAMPLES_N_MASK			0x00000003
#define		MSAA_SAMPLES_N_SHIFT			0
#define PA_SU_VTX_CTL				0x28c08
#define PA_CL_GB_V_CLIP_ADJ			0x28c0c
#define PA_CL_GB_V_DISC_ADJ			0x28c10
#define PA_CL_GB_H_CLIP_ADJ			0x28c14
#define PA_CL_GB_H_DISC_ADJ			0x28c18
#define PA_SC_AA_SAMPLE_LOCS_0			0x28c1c
#define PA_SC_AA_SAMPLE_LOCS_1			0x28c20
#define PA_SC_AA_SAMPLE_LOCS_2			0x28c24
#define PA_SC_AA_SAMPLE_LOCS_3			0x28c28
#define PA_SC_AA_SAMPLE_LOCS_4			0x28c2c
#define PA_SC_AA_SAMPLE_LOCS_5			0x28c30
#define PA_SC_AA_SAMPLE_LOCS_6			0x28c34
#define PA_SC_AA_SAMPLE_LOCS_7			0x28c38
#define PA_SC_AA_MASK				0x28c3c

#define	VGT_VTX_REUSE_BLK_CTL			0x28c58
#define		VTX_REUSE_DEPTH_MASK			0x000000ff
#define	VGT_OUT_DEALLOC_CTL			0x28c5c
#define		DEALLOC_DIST_MASK			0x0000007f
#define	CB_COLOR_0_BASE				0x28c60
#define	CB_COLOR_0_PITCH			0x28c64
#define	CB_COLOR_0_SLICE			0x28c68
#define	CB_COLOR_0_VIEW				0x28c6c
#define		SLICE_START_MASK			0x7ff
#define		SLICE_START_SHIFT			0
#define		SLICE_MAX_MASK				0x00ffe000
#define		SLICE_MAX_SHIFT				13
#define CB_COLOR_0_INFO				0x28c70
#define		CB_ENDIAN_MASK				0x00000003
#define		CB_ENDIAN_SHIFT				0
#define		CB_FMT_MASK				0x000000fc
#define		CB_FMT_SHIFT				2
#define			COLOR_INVALID				0x00
#define			COLOR_8					0x01
#define			COLOR_4_4				0x02
#define			COLOR_3_3_2				0x03
#define			COLOR_16				0x05
#define			COLOR_16_FLOAT				0x06
#define			COLOR_8_8				0x07
#define			COLOR_5_6_5				0x08
#define			COLOR_6_5_5				0x09
#define			COLOR_1_5_5_5				0x0a
#define			COLOR_4_4_4_4				0x0b
#define			COLOR_5_5_5_1				0x0c
#define			COLOR_32				0x0d
#define			COLOR_32_FLOAT				0x0e
#define			COLOR_16_16				0x0f
#define			COLOR_16_16_FLOAT			0x10
#define			COLOR_8_24				0x11
#define			COLOR_8_24_FLOAT			0x12
#define			COLOR_24_8				0x13
#define			COLOR_24_8_FLOAT			0x14
#define			COLOR_10_11_11				0x15
#define			COLOR_10_11_11_FLOAT			0x16
#define			COLOR_11_11_10				0x17
#define			COLOR_11_11_10_FLOAT			0x18
#define			COLOR_2_10_10_10			0x19
#define			COLOR_8_8_8_8				0x1a
#define			COLOR_10_10_10_2			0x1b
#define			COLOR_X24_8_32_FLOAT			0x1c
#define			COLOR_32_32				0x1d
#define			COLOR_32_32_FLOAT			0x1e
#define			COLOR_16_16_16_16			0x1f
#define			COLOR_16_16_16_16_FLOAT			0x20
#define			COLOR_32_32_32_32			0x22
#define			COLOR_32_32_32_32_FLOAT			0x23
#define			COLOR_32_32_32_FLOAT			0x30
#define		CB_ARRAY_MODE_MASK				0x00000f00
#define		CB_ARRAY_MODE_SHIFT				8	
#define			ARRAY_LINEAR_GENERAL			0
#define			ARRAY_LINEAR_ALIGNED			1
#define			ARRAY_1D_TILED_THIN1			2
#define			ARRAY_2D_TILED_THIN1			4
#define		CB_NUM_TYPE_MASK			0x00007000
#define		CB_NUM_TYPE_SHIFT			12
#define			NUM_UNNORM				0
#define			NUM_SNORM				1
#define			NUM_USCALED				2
#define			NUM_SSCALED				3
#define			NUM_UINT				4
#define			NUM_SINT				5
#define			NUM_SRGB				6
#define			NUM_FLOAT				7
#define		COMP_SWAP_MASK				0x00018000
#define		COMP_SWAP_SHIFT				15
#define			SWAP_STD				0
#define			SWAP_ALT				1
#define			SWAP_STD_REV				2
#define			SWAP_ALT_REV				3
#define		FAST_CLR				BIT(17)
#define		COMP_MASK				0x000c00000
#define		COMP_SHIFT				18
#define		BLEND_CLAMP				BIT(19)
#define		BLEND_BYPASS				BIT(20)
#define		SIMPLE_FLOAT				BIT(21)
#define		ROUND_MODE				BIT(22)
#define		TILE_COMPACT				BIT(23)
#define		CB_SRC_FMT_MASK				0x03000000
#define		CB_SRC_FMT_SHIFT			24
#define			EXPORT_4C_32BPC				0
#define			EXPORT_FULL				0/* 2 names */
#define			EXPORT_4C_16BPC				1
#define			EXPORT_NORM				1/* 2 names */
#define			EXPORT_2C_32BPC				2/* do not use*/
#define		RAT					BIT(26)
#define		RES_TYPE_MASK				0x38000000
#define		RES_TYPE_SHIFT				27
#define CB_COLOR_0_ATTRIB			0x28c74
#define		NON_DISP_TILING_ORDER			BIT(4)
#define		CB_TILE_SPLIT_MASK			0x000001e0
#define		CB_TILE_SPLIT_SHIFT			5
#define			ADDR_SURF_TILE_SPLIT_64B		0
#define			ADDR_SURF_TILE_SPLIT_128B		1
#define			ADDR_SURF_TILE_SPLIT_256B		2
#define			ADDR_SURF_TILE_SPLIT_512B		3
#define			ADDR_SURF_TILE_SPLIT_1KB		4
#define			ADDR_SURF_TILE_SPLIT_2KB		5
#define			ADDR_SURF_TILE_SPLIT_4KB		6
#define		BANKS_N_MASK				0x00000c00
#define		BANKS_N_SHIFT				10
#define			ADDR_SURF_2_BANK			0
#define			ADDR_SURF_4_BANK			1
#define			ADDR_SURF_8_BANK			2
#define			ADDR_SURF_16_BANK			3
#define		BANK_W_MASK				0x00006000
#define		BANK_W_SHIFT				13
#define			ADDR_SURF_BANK_W_1			0
#define			ADDR_SURF_BANK_W_2			1
#define			ADDR_SURF_BANK_W_4			2
#define			ADDR_SURF_BANK_W_8			3
#define		BANK_H_MASK				0x00030000
#define		BANK_H_SHIFT				16
#define			ADDR_SURF_BANK_H_1			0
#define			ADDR_SURF_BANK_H_2			1
#define			ADDR_SURF_BANK_H_4			2
#define			ADDR_SURF_BANK_H_8			3
#define		CB_MACRO_TILE_ASPECT_MASK		0x00180000
#define		CB_MACRO_TILE_ASPECT_SHIFT		19
#define	CB_COLOR_0_DIM				0x28c78
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_0_CMASK			0x28c7c
#define	CB_COLOR_0_CMASK_SLICE			0x28c80
#define	CB_COLOR_0_FMASK			0x28c84
#define	CB_COLOR_0_FMASK_SLICE			0x28c88
#define CB_COLOR_0_CLR_WD_0			0x28c8c
#define CB_COLOR_0_CLR_WD_1			0x28c90
#define CB_COLOR_0_CLR_WD_2			0x28c94
#define CB_COLOR_0_CLR_WD_3			0x28c98
#define	CB_COLOR_1_BASE				0x28c9c
#define	CB_COLOR_1_PITCH			0x28ca0
#define	CB_COLOR_1_SLICE			0x28ca4
#define	CB_COLOR_1_VIEW				0x28ca8
#define CB_COLOR_1_INFO				0x28cac
#define CB_COLOR_1_ATTRIB			0x28cb0
#define CB_COLOR_1_DIM				0x28cb4
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_1_CMASK			0x28cb8
#define	CB_COLOR_1_CMASK_SLICE			0x28cbc
#define	CB_COLOR_1_FMASK			0x28cc0
#define	CB_COLOR_1_FMASK_SLICE			0x28cc4
#define CB_COLOR_1_CLR_WD_0			0x28cc8
#define CB_COLOR_1_CLR_WD_1			0x28ccc
#define CB_COLOR_1_CLR_WD_2			0x28cd0
#define CB_COLOR_1_CLR_WD_3			0x28cd4
#define	CB_COLOR_2_BASE				0x28cd8
#define	CB_COLOR_2_PITCH			0x28cdc
#define	CB_COLOR_2_SLICE			0x28ce0
#define	CB_COLOR_2_VIEW				0x28ce4
#define CB_COLOR_2_INFO				0x28ce8
#define CB_COLOR_2_ATTRIB			0x28cec
#define CB_COLOR_2_DIM				0x28cf0
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_2_CMASK			0x28cf4
#define	CB_COLOR_2_CMASK_SLICE			0x28cf8
#define	CB_COLOR_2_FMASK			0x28cfc
#define	CB_COLOR_2_FMASK_SLICE			0x28d00
#define CB_COLOR_2_CLR_WD_0			0x28d04
#define CB_COLOR_2_CLR_WD_1			0x28d08
#define CB_COLOR_2_CLR_WD_2			0x28d0c
#define CB_COLOR_2_CLR_WD_3			0x28d10
#define	CB_COLOR_3_BASE				0x28d14
#define	CB_COLOR_3_PITCH			0x28d18
#define	CB_COLOR_3_SLICE			0x28d1c
#define	CB_COLOR_3_VIEW				0x28d20
#define CB_COLOR_3_INFO				0x28d24
#define CB_COLOR_3_ATTRIB			0x28d28
#define CB_COLOR_3_DIM				0x28d2c
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_3_CMASK			0x28d30
#define	CB_COLOR_3_CMASK_SLICE			0x28d34
#define	CB_COLOR_3_FMASK			0x28d38
#define	CB_COLOR_3_FMASK_SLICE			0x28d3c
#define CB_COLOR_3_CLR_WD_0			0x28d40
#define CB_COLOR_3_CLR_WD_1			0x28d44
#define CB_COLOR_3_CLR_WD_2			0x28d48
#define CB_COLOR_3_CLR_WD_3			0x28d4c
#define	CB_COLOR_4_BASE				0x28d50
#define	CB_COLOR_4_PITCH			0x28d54
#define	CB_COLOR_4_SLICE			0x28d58
#define	CB_COLOR_4_VIEW				0x28d5c
#define CB_COLOR_4_INFO				0x28d60
#define CB_COLOR_4_ATTRIB			0x28d64
#define CB_COLOR_4_DIM				0x28d68
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_4_CMASK			0x28d6c
#define	CB_COLOR_4_CMASK_SLICE			0x28d70
#define	CB_COLOR_4_FMASK			0x28d74
#define	CB_COLOR_4_FMASK_SLICE			0x28d78
#define CB_COLOR_4_CLR_WD_0			0x28d7c
#define CB_COLOR_4_CLR_WD_1			0x28d80
#define CB_COLOR_4_CLR_WD_2			0x28d84
#define CB_COLOR_4_CLR_WD_3			0x28d88
#define	CB_COLOR_5_BASE				0x28d8c
#define	CB_COLOR_5_PITCH			0x28d90
#define	CB_COLOR_5_SLICE			0x28d94
#define	CB_COLOR_5_VIEW				0x28d98
#define CB_COLOR_5_INFO				0x28d9c
#define CB_COLOR_5_ATTRIB			0x28da0
#define CB_COLOR_5_DIM				0x28da4
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_5_CMASK			0x28da8
#define	CB_COLOR_5_CMASK_SLICE			0x28dac
#define	CB_COLOR_5_FMASK			0x28db0
#define	CB_COLOR_5_FMASK_SLICE			0x28db4
#define CB_COLOR_5_CLR_WD_0			0x28db8
#define CB_COLOR_5_CLR_WD_1			0x28dbc
#define CB_COLOR_5_CLR_WD_2			0x28dc0
#define CB_COLOR_5_CLR_WD_3			0x28dc4
#define	CB_COLOR_6_BASE				0x28dc8
#define	CB_COLOR_6_PITCH			0x28dcc
#define	CB_COLOR_6_SLICE			0x28dd0
#define	CB_COLOR_6_VIEW				0x28dd4
#define CB_COLOR_6_INFO				0x28dd8
#define CB_COLOR_6_ATTRIB			0x28ddc
#define CB_COLOR_6_DIM				0x28de0
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_6_CMASK			0x28de4
#define	CB_COLOR_6_CMASK_SLICE			0x28de8
#define	CB_COLOR_6_FMASK			0x28dec
#define	CB_COLOR_6_FMASK_SLICE			0x28df0
#define CB_COLOR_6_CLR_WD_0			0x28df4
#define CB_COLOR_6_CLR_WD_1			0x28df8
#define CB_COLOR_6_CLR_WD_2			0x28dfc
#define CB_COLOR_6_CLR_WD_3			0x28e00
#define	CB_COLOR_7_BASE				0x28e04
#define	CB_COLOR_7_PITCH			0x28e08
#define	CB_COLOR_7_SLICE			0x28e0c
#define	CB_COLOR_7_VIEW				0x28e10
#define CB_COLOR_7_INFO				0x28e14
#define CB_COLOR_7_ATTRIB			0x28e18
#define CB_COLOR_7_DIM				0x28e1c
/* only CB0-7 blocks have the 4 following regs */
#define	CB_COLOR_7_CMASK			0x28e20
#define	CB_COLOR_7_CMASK_SLICE			0x28e24
#define	CB_COLOR_7_FMASK			0x28e28
#define	CB_COLOR_7_FMASK_SLICE			0x28e2c
#define CB_COLOR_7_CLR_WD_0			0x28e30
#define CB_COLOR_7_CLR_WD_1			0x28e34
#define CB_COLOR_7_CLR_WD_2			0x28e38
#define CB_COLOR_7_CLR_WD_3			0x28e3c
#define	CB_COLOR_8_BASE				0x28e40
#define	CB_COLOR_8_PITCH			0x28e44
#define	CB_COLOR_8_SLICE			0x28e48
#define	CB_COLOR_8_VIEW				0x28e4c
#define CB_COLOR_8_INFO				0x28e50
#define CB_COLOR_8_ATTRIB			0x28e54
#define CB_COLOR_8_DIM				0x28e58
#define	CB_COLOR_9_BASE				0x28e5c
#define	CB_COLOR_9_PITCH			0x28e60
#define	CB_COLOR_9_SLICE			0x28e64
#define	CB_COLOR_9_VIEW				0x28e68
#define CB_COLOR_9_INFO				0x28e6c
#define CB_COLOR_9_ATTRIB			0x28e70
#define CB_COLOR_9_DIM				0x29e74
#define	CB_COLOR_A_BASE				0x28e78
#define	CB_COLOR_A_PITCH			0x28e7c
#define	CB_COLOR_A_SLICE			0x28e80
#define	CB_COLOR_A_VIEW				0x28e84
#define CB_COLOR_A_INFO				0x28e88
#define CB_COLOR_A_ATTRIB			0x28e8c
#define CB_COLOR_A_DIM				0x28e90
#define	CB_COLOR_B_BASE				0x28e94
#define	CB_COLOR_B_PITCH			0x28e98
#define	CB_COLOR_B_SLICE			0x28e9c
#define	CB_COLOR_B_VIEW				0x28ea0
#define CB_COLOR_B_INFO				0x28ea4
#define CB_COLOR_B_ATTRIB			0x28ea8
#define CB_COLOR_B_DIM				0x28eac

#define SQ_ALU_CONST_BUF_SZ_HS_0		0x28f80
#define SQ_ALU_CONST_BUF_SZ_HS_1		0x28f84
#define SQ_ALU_CONST_BUF_SZ_HS_2		0x28f88
#define SQ_ALU_CONST_BUF_SZ_HS_3		0x28f8c
#define SQ_ALU_CONST_BUF_SZ_HS_4		0x28f90
#define SQ_ALU_CONST_BUF_SZ_HS_5		0x28f94
#define SQ_ALU_CONST_BUF_SZ_HS_6		0x28f98
#define SQ_ALU_CONST_BUF_SZ_HS_7		0x28f9c
#define SQ_ALU_CONST_BUF_SZ_HS_8		0x28fa0
#define SQ_ALU_CONST_BUF_SZ_HS_9		0x28fa4
#define SQ_ALU_CONST_BUF_SZ_HS_A		0x28fa8
#define SQ_ALU_CONST_BUF_SZ_HS_B		0x28fac
#define SQ_ALU_CONST_BUF_SZ_HS_C		0x28fb0
#define SQ_ALU_CONST_BUF_SZ_HS_D		0x28fb4
#define SQ_ALU_CONST_BUF_SZ_HS_E		0x28fb8
#define SQ_ALU_CONST_BUF_SZ_HS_F		0x28fbc
#define SQ_ALU_CONST_BUF_SZ_LS_0		0x28fc0
#define SQ_ALU_CONST_BUF_SZ_LS_1		0x28fc4
#define SQ_ALU_CONST_BUF_SZ_LS_2		0x28fc8
#define SQ_ALU_CONST_BUF_SZ_LS_3		0x28fcc
#define SQ_ALU_CONST_BUF_SZ_LS_4		0x28fd0
#define SQ_ALU_CONST_BUF_SZ_LS_5		0x28fd4
#define SQ_ALU_CONST_BUF_SZ_LS_6		0x28fd8
#define SQ_ALU_CONST_BUF_SZ_LS_7		0x28fdc
#define SQ_ALU_CONST_BUF_SZ_LS_8		0x28fe0
#define SQ_ALU_CONST_BUF_SZ_LS_9		0x28fe4
#define SQ_ALU_CONST_BUF_SZ_LS_A		0x28fe8
#define SQ_ALU_CONST_BUF_SZ_LS_B		0x28fec
#define SQ_ALU_CONST_BUF_SZ_LS_C		0x28ff0
#define SQ_ALU_CONST_BUF_SZ_LS_D		0x28ff4
#define SQ_ALU_CONST_BUF_SZ_LS_E		0x28ff8
#define SQ_ALU_CONST_BUF_SZ_LS_F		0x28ffc

/* start of resource area: 0x30000-0x38000 */
#define SQ_TEX_RES_WD_0_0			0x30000
#define		TEX_DIM_MASK				0xffffffff
#define		TEX_DIM_SHIFT				0
#define			SQ_TEX_DIM_1D				0
#define			SQ_TEX_DIM_2D				1
#define			SQ_TEX_DIM_3D				2
#define			SQ_TEX_DIM_CUBEMAP			3
#define			SQ_TEX_DIM_1D_ARRAY			4
#define			SQ_TEX_DIM_2D_ARRAY			5
#define			SQ_TEX_DIM_2D_MSAA			6
#define			SQ_TEX_DIM_2D_ARRAY_MSAA		7
/* aligned on 4 pitch unit - 1 */
#define		TEX_PITCH_MASK				0xffffffff
#define		TEX_PITCH_SHIFT				6
/* w - 1 */
#define		TEX_W_MASK				0xffffffff
#define		TEX_W_SHIFT				18
#define SQ_TEX_RES_WD_1_0			0x30004
/* h - 1 */
#define		TEX_H_MASK				0xffffffff
#define		TEX_H_SHIFT				0
#define		TEX_ARRAY_MODE_MASK			0xffffffff
#define		TEX_ARRAY_MODE_SHIFT			28
#define SQ_TEX_RES_WD_2_0			0x30008
#define SQ_TEX_RES_WD_3_0			0x3000c
#define SQ_TEX_RES_WD_4_0			0x30010
#define		TEX_DST_SEL_X_MASK			0xffffffff
#define		TEX_DST_SEL_X_SHIFT			16
#define		TEX_DST_SEL_Y_MASK			0xffffffff
#define		TEX_DST_SEL_Y_SHIFT			19
#define		TEX_DST_SEL_Z_MASK			0xffffffff
#define		TEX_DST_SEL_Z_SHIFT			22
#define		TEX_DST_SEL_W_MASK			0xffffffff
#define		TEX_DST_SEL_W_SHIFT			25
#define			SQ_SEL_X					0
#define			SQ_SEL_Y					1
#define			SQ_SEL_Z					2
#define			SQ_SEL_W					3
#define			SQ_SEL_0					4
#define			SQ_SEL_1					5
#define SQ_TEX_RES_WD_5_0			0x30014
#define SQ_TEX_RES_WD_6_0			0x30018
#define		TEX_TILE_SPLIT_MASK			0xe0000000
#define		TEX_TILE_SPLIT_SHIFT			29
#define SQ_TEX_RES_WD_7_0			0x3001c
#define		MACRO_TILE_ASPECT_MASK			0x000000c0
#define		MACRO_TILE_ASPECT_SHIFT			6
#define		TEX_BANK_W_MASK				0x00000300
#define		TEX_BANK_W_SHIFT			8
#define		TEX_BANK_H_MASK				0x00000c00
#define		TEX_BANK_H_SHIFT			10
#define		TEX_BANKS_N_MASK			0x00030000
#define		TEX_BANKS_N_SHIFT			16
#define		SQ_CONST_TYPE_MASK			0xc0000000
#define		SQ_CONST_TYPE_SHIFT			30
#define			SQ_TEX_VTX_INVALID_TEX			0
#define			SQ_TEX_VTX_INVALID_BUF			1
#define			SQ_TEX_VTX_VALID_TEX			2
#define			SQ_TEX_VTX_VALID_BUF			3

/* start of sampler register area: 0x3c000-0x3c600 */

/* start of const register area: 0x3cff0-0x3ff0c */
#define SQ_VTX_BASE_VTX_LOC			0x3cff0
#define SQ_VTX_START_INST_LOC			0x3cff4

#define SQ_TEX_SAMPLER_CLR			0x3ff00
#define SQ_TEX_RESOURCE_CLR			0x3ff04
#define SQ_LOOP_BOOL_CLR			0x3ff08
#endif
